 //=================================================================================================
// Register Set
//=================================================================================================

		#define	r0				%0
		#define	r1				%1
		#define	r2				%2
		#define	r3				%3
		#define	r4				%4
		#define	r5				%5
		#define	r6				%6
		#define	r7				%7
		#define	sp				%7

//=================================================================================================
// Conditional Branch Tests
//=================================================================================================

// 	Test NZVC Bits (Clear or Set)
//		#define	NC				0xB
//		#define	NS				0x3
//		#define	ZC				0xA
//		#define	ZS				0x2
//		#define	VC				0x9
//		#define	VS				0x1
//		#define	CC				0x8
//		#define	CS				0x0
//
//	Comparison
//		#define	EQ				0x2
//		#define	NE				0xA
//
//		#define	LT0				0x3
//		#define	LE0				0x7
//		#define	GE0				0xB
//		#define	GT0				0xF
//
//	Signed Comparison
//		#define	LT				0x5
//		#define	LE				0x6
//		#define	GE				0xD
//		#define	GT				0xE
//
//	Unsigned Comparison
//		#define	ULT				0x0
//		#define	ULE				0x4
//		#define	UGE				0x8
//		#define	UGT				0xC

//=================================================================================================
// I/O Peripheral Addresses common to both iopage = 0 and iopage = 1
//=================================================================================================

	// SCU (Supervisory Control Unit)
		#define	SCUreg			0x00
		#define	SCUpc				0x01
		#define	SCUcc				0x02
		#define	SCUtime			0x03
		#define	SCUpntr			0x03
		#define	SCUbkpt			0x04
		#define	SCUstop			0x04
		#define	SCUwait			0x05
		#define	SCUiopageWR			0x05
		#define	SCUrsrc			0x06
		#define	SCUup				0x06
		#define	SCUiopageRD			0x07
		#define	SCUdown			0x07


	//LFSR0 (Linear Feedback Shift Register)
		#define	LFSR0cfg			0x08
		#define	LFSR0tapcfg			0x09
		#define	LFSR0reg			0x0A
		#define	LFSR0data			0x0B

	//LFSR1 (Linear Feedback Shift Register)
		#define	LFSR1cfg			0x0C
		#define	LFSR1tapcfg			0x0D
		#define	LFSR1reg			0x0E
		#define	LFSR1data			0x0F

	//VPU (Vector Processing Unit)

		#define	VPUcfg0			0x10
		#define	VPUcfg1			0x11
		#define	VPUopAba			0x12
		#define	VPUopBba			0x13
		#define	VPUopadrmsk			0x14
		#define	VPUopA			0x15
		#define	VPUopB			0x16
		#define	VPUrsba			0x17
		#define	VPUrsadrsmk			0x18
		#define	VPUrslsw			0x19
		#define	VPUrsmsw			0x1A
		#define	VPUrsext			0x1B
		#define	VPUfilterLength		0x1C

	// SPI0 (Serial Peripheral Interface)
		#define	SPI0rx			0x34
		#define	SPI0tx			0x34
		#define	SPI0cfg			0x35

	// SPI1 (Serial Peripheral Interface)
		#define	SPI1rx			0x36
		#define	SPI1tx			0x36
		#define	SPI1cfg			0x37

	// SFU (Shared Functional Units)
		#define	SFUrev			0x38
		#define	SFUpack			0x39
		#define	SFUpop			0x3A
		#define	SFUls1			0x3B

	// TMRA (TimerA)
		#define	TMRAcfg			0x3E
		#define	TMRAcount			0x3F
		#define	TMRACCR0			0x40
		#define	TMRACCM0cfg			0x41
		#define	TMRACCR1			0x42
		#define	TMRACCM1cfg			0x43
		#define	TMRACCR2			0x44
		#define	TMRACCM2cfg			0x45
		#define	TMRACCR3			0x46
		#define	TMRACCM3cfg			0x47


	// GPIO (General Purpose I/O)
   		#define	GPAin				0x20
		#define	GPAout			0x20
		#define	GPAcfg			0x21

		#define	GPBin				0x22
		#define	GPBout			0x22
		#define	GPBcfg			0x23

		#define	GPCin				0x24
		#define	GPCout			0x24
		#define	GPCcfg			0x25

		#define	GPDin				0x26
		#define	GPDout			0x26
		#define	GPDcfg			0x27

		#define	GPEin				0x28
		#define	GPEout			0x28
		#define	GPEcfg			0x29

		#define	GPFin				0x2A
		#define	GPFout			0x2A
		#define	GPFcfg			0x2B

		#define	GPGin				0x2C
		#define	GPGout			0x2C
		#define	GPGcfg			0x2D

		#define	GPHin				0x2E
		#define	GPHout			0x2E
		#define	GPHcfg			0x2F

		#define	GPIin				0x30
		#define	GPIout			0x30
		#define	GPIcfg			0x31

		#define	GPJin				0x32
		#define	GPJout			0x32
		#define	GPJcfg			0x33


//=================================================================================================
// I/O Peripheral Addresses for iopage = 0
//=================================================================================================

	// TMRB (TimerB)
		#define	TMRBcfg			0x48
		#define	TMRBcount			0x49
		#define	TMRBCCR0			0x4A
		#define	TMRBCCM0cfg			0x4B
		#define	TMRBCCR1			0x4C
		#define	TMRBCCM1cfg			0x4D



	// XInC1 BBU names for ease of use with XInC1 code
		#define	BBUcfg			0x58
		#define	BBUstatus			0x58
		#define	BBUtx				0x5A
		#define	BBUrx				0x5A
		#define	BBUbrg			0x5B
		#define	BBUtime			0x5C
		#define	BBUrx4			0x5D
		#define	BBUrx6			0x5E
		#define	BBUstart			0x5F


	// BBU0
		#define	BBU0cfg0			0x58
		#define	BBU0cfg1 			0x59
		#define	BBU0tx			0x5A
		#define	BBU0rx			0x5A
		#define	BBU0brg			0x5B
		#define	BBU0time			0x5C
		#define	BBU0rx4			0x5D
		#define	BBU0rx6			0x5E
		#define	BBU0start			0x5F

	// BBU1
		#define	BBU1cfg0			0x60
		#define	BBU1cfg1 			0x61
		#define	BBU1tx			0x62
		#define	BBU1rx			0x62
		#define	BBU1brg			0x63
		#define	BBU1time			0x64
		#define	BBU1flow			0x65
		#define	BBU1rx4			0x65
		#define	BBU1start			0x67

	// DASI (Digital Audio Serial Interface)
		#define	DASIconfig0			0x68
		#define	DASIconfig1			0x69
		#define	DASIconfig2			0x6A
		#define	DASIstatus0			0x6B
		#define	DASIstatus1			0x6C
		#define	DASIstatus2			0x6D

	       #define    DASIrx0         	   	0x6B
	       #define    DASIrx1         	   	0x6C
	       #define    DASIrx2         	   	0x6D
	       #define    DASItx0            	0x6B
	       #define    DASItx1            	0x6C
	       #define    DASItx2            	0x6D
	       #define	DASIcount0			0x6E
	       #define	DASIcount1			0x6F



	// SCX (Supervisory Control Extensions)
		#define	SCXioCfgP			0x70
		#define	SCXioCfgD			0x71

		#define	SCXclkCfg			0x72
		#define	SCXaltCfg			0x73
		#define	SCXPLLCfg0			0x74
		#define	SCXPLLCfg1			0x75
		#define	SCXmemcol			0x76
		#define	SCXcount			0x77

	// SMU (Sleep Mode Unit)
		#define	SMUcfg0			0x78
		#define	SMUcfg1			0x79

	//ADC
	     #define      ADCcfg0			0x7D
	     #define      ADCcfg1			0x7E
	     #define      ADCdata			0x7F 
           
//	     #define      ADCcfg0			BBU1start
//	     #define      ADCcfg1			BBU1start
//	     #define      ADCdata			BBU1start  

//=================================================================================================
// I/O Peripheral Addresses for iopage = 1
//=================================================================================================

	// Quant0 (ADPCM Difference Quantizer)
		#define	Quant0cfg			0x48
		#define	Quant0pred			0x49
		#define	Quant0dec			0x49
		#define	Quant0step			0x4A
		#define	Quant0delta			0x4A
		#define	Quant0samp			0x4B

	// Quant1 (ADPCM Difference Quantizer)
		#define	Quant1cfg			0x4C
		#define	Quant1pred			0x4D
		#define	Quant1dec			0x4D
		#define	Quant1step			0x4E
		#define	Quant1delta			0x4E
		#define	Quant1samp			0x4F

	// Quant2 (ADPCM Difference Quantizer)
		#define	Quant2cfg			0x50
		#define	Quant2pred			0x51
		#define	Quant2dec			0x51
		#define	Quant2step			0x52
		#define	Quant2delta			0x52
		#define	Quant2samp			0x53

	// Quant3 (ADPCM Difference Quantizer)
		#define	Quant3cfg			0x54
		#define	Quant3pred			0x55
		#define	Quant3dec			0x55
		#define	Quant3step			0x56
		#define	Quant3delta			0x56
		#define	Quant3samp			0x57

	// InvQuant0 (ADPCM Inverse Difference Quantizer)
		#define	InvQuant0cfg		0x58
		#define	InvQuant0delta		0x59
		#define	InvQuant0vpdiff		0x59
		#define	InvQuant0step		0x5A

	// InvQuant1 (ADPCM Inverse Difference Quantizer)
		#define	InvQuant1cfg		0x5C
		#define	InvQuant1delta		0x5D
		#define	InvQuant1vpdiff		0x5D
		#define	InvQuant1step		0x5E

	// InvQuant2 (ADPCM Inverse Difference Quantizer)
		#define	InvQuant2cfg		0x60
		#define	InvQuant2delta		0x61
		#define	InvQuant2vpdiff		0x61
		#define	InvQuant2step		0x62

	// InvQuant3 (ADPCM Inverse Difference Quantizer)
		#define	InvQuant3cfg		0x64
		#define	InvQuant3delta		0x65
		#define	InvQuant3vpdiff		0x65
		#define	InvQuant3step		0x66

	// Accum0 (Accumulator)
		#define	Accum0cfg			0x68
		#define	Accum0high			0x69
		#define	Accum0low			0x6A
		#define	Accum0addsubhigh		0x6B
		#define	Accum0addlow		0x6C
		#define	Accum0sublow		0x6D

	// Accum1 (Accumulator)
		#define	Accum1cfg			0x6E
		#define	Accum1high			0x6F
		#define	Accum1low			0x70
		#define	Accum1addsubhigh		0x71
		#define	Accum1addlow		0x72
		#define	Accum1sublow		0x73



//ADC Configuration
		#define 	ADC_ENABLE			15
		#define 	ADC_CLK_DIV			12
		#define 	ADC_START			9
		#define	MUX_ENABLE			0
		
//VPU configuration0 register bit definitions
		#define	clrA		15	//clear accumuluator(WRITE ONLY)
		#define	clraaOPB	14	//USE FOR VECTOR MAC clear OPBa
		#define	addnsubCfg	13	//add/subtract mode
		#define	RSh		12	//result shift config
		#define	Rinc		11	//increment Result base address
		#define	Binc		10	//increment OPB base address
		#define	ADec		9	//decimation mode
		#define	Ainc		8	//increment OPA base address
		#define	ACcfg		7	//accumulaor source config
		#define	aB		6	//adder operandB config
		#define	aA		5	//adder operandA config
		#define	DFW		3	//data field to write
		#define	Rdest		2	//result memory destination
		#define	OPsrc		0	//operand source configuration

//VPU configuration1 register bit definitions
		#define	Pipe		7	//piple line enable
		#define	RS		5	//Result saturation
		#define	RR		4	//result rounding
		#define	AddAlign	3	//configure alignemnt of operands for add operation
		#define	MS		2	//multiplier shift
		#define	Btyp		1	//operand B type
		#define	Atyp		0	//operand A type


// ASCII dffines                                               
		#define	EOS				0	// End Of String  
		#define	BS				8	// Back Space     
		#define	LF				10	// Line Feed      
		#define	CR				13	// Carriage Return

//Serial interface Routines in MaskROM
		#define 	XPD_MiniEcho           	0x1800
		#define 	XPD_MiniEcho_RW        	0x1808
		#define 	UnsignedDivide         	0x1816
		#define 	XPD_WriteByte          	0x1867
		#define 	XPD_ReadByte           	0x1878
		#define 	XPD_ReadByteWithTimeout	0x1884
		#define 	XPD_ReadWriteByte      	0x1898
		#define 	XPD_ShiftInOut         	0x18A9
		#define 	XPD_EchoString         	0x18BB
		#define 	XPD_EchoUnsignedDec    	0x18CB
		#define 	XPD_EchoSignedDec      	0x1929
		#define 	XPD_EchoHex            	0x19B3
		#define 	XPD_EchoHexNP          	0x19C1
		#define 	XPD_EchoHexByte        	0x19E7
		#define 	XPD_EchoHexByteNP      	0x19F5
		#define 	XPD_EchoSetBitList     	0x1A0D
		#define 	XPD_EchoBlock          	0x1A32

		